Von Neumann Architecture
📌 Based on a design from the mid-1940s, it uses a single memory space for both instructions and data.
⚙️ Key components include the CPU, memory unit, I/O system, and control unit, utilizing an ALU for operations.
⏳ The shared memory bus results in the Von Neumann bottleneck, limiting concurrent instruction fetching and data transfer.

Harvard Architecture
🔗 Defined by using separate memory spaces and dedicated buses for instructions and data.
⚡ This separation allows simultaneous fetching of instructions and access to data, leading to higher throughput than Von Neumann systems.
💡 Commonly employed in embedded systems, microcontrollers, and Digital Signal Processors (DSPs) for predictable performance.

CISC (Complex Instruction Set Computer)
🧩 Features a large set of instructions, where single commands can perform multi-step operations (e.g., load, calculate, store).
💾 The goal was to simplify programming and reduce program size when memory was expensive, heavily relying on microcode translation.
🖥️ The x86 architecture, dominant in desktop and laptop PCs, is the most recognized CISC implementation.

RISC (Reduced Instruction Set Computer)
🔄 Employs a small, highly optimized set of instructions, aiming for most instructions to execute in a single clock cycle.
🧱 Key principles include a load-store architecture and uniform instruction length for pipeline efficiency.
📱 The ARM architecture is the dominant RISC design, powering smartphones and increasingly modern laptops due to its efficiency.

EPIC (Explicitly Parallel Instruction Computing)
🔠 Relies on the compiler to identify and explicitly mark instructions that can run in parallel for the CPU.
🛡️ Introduced features like predicated execution (conditional instruction execution) and speculative loading to reduce pipeline stalls.
📉 The Intel Itanium implementation ultimately failed in the mass market due to compiler limitations and slow adoption.

Superscalar Architecture
🧠 Allows the processor to execute multiple instructions per clock cycle by employing multiple execution units concurrently.
🔄 Uses complex hardware mechanisms like out-of-order execution and branch prediction to manage instruction dependencies.
📈 This design has been the primary driver of performance scaling in general-purpose CPUs since the 1990s.

Multi-Core and Many-Core CPUs
🛠️ A multi-core CPU places multiple independent processing units on one chip, boosting performance through parallelism (e.g., quad-core running four threads).
🔥 The shift to multi-core began in the mid-2000s because increasing clock speeds became impractical due to heat and power consumption.
🖥️ Server and HPC systems utilize many-core CPUs (dozens or hundreds of cores) for highly parallel workloads like scientific simulations.

Hybrid Architectures
🧩 Combines different core types on a single chip, such as powerful "big" cores and energy-efficient "little" cores (e.g., ARM's big.LITTLE).
🔋 The operating system dynamically switches workloads between core types to optimize for performance or battery life.
🍎 Apple's M-series processors leverage this hybrid approach with performance and efficiency cores, leading to strong performance per watt.

Key Points & Insights
➡️ The Von Neumann bottleneck stems from instructions and data sharing a single bus, limiting concurrent operations.
➡️ RISC philosophy prioritizes simple, fast-executing instructions, making it ideal for mobile efficiency (ARM).
➡️ Superscalar designs utilize multiple execution units and out-of-order processing to boost single-thread performance.
➡️ Hybrid architectures offer flexibility by matching task demands to the most suitable core type (performance vs. efficiency).

📸 Video summarized with SummaryTube.com on Nov 16, 2025, 14:21 UTC