Rangkaian Half Adder - Full Adder - Parallel Adder

Half Adder (HA) Circuit
📌 The Half Adder has two inputs (A and B, 1-bit) and two outputs: Sum (S) and Carry (C).
⚙️ It is limited because it cannot handle a carry-in from a previous bit addition (e.g., adding three 1-bit inputs).
💡 The Sum output is achieved using an Exclusive OR (XOR) gate, and the Carry output is generated using an AND gate (A $\cdot$ B).

Full Adder (FA) Circuit
📌 The Full Adder is more complex, accepting three inputs: A, B, and Carry-In ($\text{C}_{\text{in}}$), producing Sum (S) and Carry-Out ($\text{C}_{\text{out}}$).
🧮 The Full Adder truth table has 8 possible input combinations (from 000 to 111).
🔗 To generate the Sum, the circuit uses a double XOR configuration ($\text{(A} \oplus \text{B)} \oplus \text{C}_{\text{in}}$).
➕ The Carry-Out logic is generated using $\text{(A} \cdot \text{B)} + (\text{(A} \oplus \text{B)} \cdot \text{C}_{\text{in}})$.

Parallel Adder Circuit
📌 A Parallel Adder (like the Ripple Carry Adder) is constructed by cascading multiple Full Adder units to handle multi-bit additions (e.g., 4-bit, 8-bit).
🔄 In this configuration, the Carry-Out ($\text{C}_{\text{out}}$) of one stage serves as the Carry-In ($\text{C}_{\text{in}}$) for the subsequent stage.
💻 Logisim software offers built-in, simplified components for $N$-bit adders, which streamline the process compared to manually connecting individual FA units.

Key Points & Insights
➡️ Start with the Half Adder (HA) to understand the basic 1-bit sum and carry generation using XOR and AND gates.
➡️ Upgrade to the Full Adder (FA) to handle the necessary third input ($\text{C}_{\text{in}}$) for sequential bit addition.
➡️ Use Parallel Adders for operations involving more than one bit, where stages are chained by connecting $\text{C}_{\text{out}}$ to the next stage's $\text{C}_{\text{in}}$.
➡️ Software Simplification: Tools like Logisim provide pre-built $N$-bit adder components, allowing immediate testing of multi-bit arithmetic without designing the entire ripple chain from discrete gates.

📸 Video summarized with SummaryTube.com on Nov 19, 2025, 04:36 UTC